View DS1337_236911.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.maxim-ic.com www.maxim-ic.com
DS1337 Serial Real-Time Clock
FEATURES
Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap-Year Compensation Valid Up to 2100 Two-Wire Serial Interface Two Time-of-Day Alarms Oscillator Stop Flag Programmable Square-Wave Output - Defaults to 32kHz on Power-Up Available in 8-Pin DIP, SO, or mSOP
GENERAL DESCRIPTION
The DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially via a 2-wire, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator.
ORDERING INFORMATION
PART DS1337 DS1337S DS1337U TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 DIP (300mil) 8 SO (150mil) 8 mSOP TOP MARK DS1337 DS1337 1337
APPLICATIONS
Handhelds (GPS, POS Terminal, MP3 Player) Consumer Electronics (Set-Top Box, VCR/Digital Recording) Office Equipment (Fax/Printer, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Router, Switcher, Server) Other (Utility Meter, Vending Machine, Thermostat, Modem)
PIN CONFIGURATIONS
TOP VIEW X1 X2 DS1337 INTA GND VCC SQW/INTB SCL SDA
TYPICAL OPERATING CIRCUIT
DIP
X1 X2 INTA GND DS1337 VCC SQW/INTB SCL SDA
SO, mSOP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 13
REV: 012003
DS1337
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.3V to +6.0V -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C) PARAMETER Supply Voltage Oscillator Voltage Logic 1 Logic 0 SYMBOL VCC VOSC VIH VIL SCL, SDA
INTA, SQW/INTB
CONDITIONS
MIN 1.8 1.3 0.7 VCC
TYP
MAX 4.0 4.0 VCC + 0.3 5.5
UNITS V V V V
-0.3
0.3 VCC
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 4.0V, TA = -40C to +85C.) PARAMETER Input Leakage I/O Leakage Logic 0 Output (VOL = 0.4V) Active Supply Current Standby Current SYMBOL ILI ILO IOL ICCA ICCS CONDITIONS (Note 1) (Note 2) (Note 2) (Note 3) (Notes 4, 5) MIN TYP MAX 1 1 3 150 2 UNITS mA mA mA mA mA
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.3V to 1.8V, TA = -40C to +85C.) PARAMETER SYMBOL Timekeeping Current (Oscillator Enabled) Data Retention Current (Oscillator Disabled) IOSC IDDR CONDITIONS (Notes 4, 6, 7) (Note 4) MIN TYP MAX 600 50 UNITS nA nA
CRYSTAL SPECIFICATIONS*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL FO ESR CL MIN TYP 32.768 6 MAX 45 UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
2 of 13
DS1337
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 4.0V, TA = -40C to +85C.) PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (Note 8) LOW Period of SCL Clock HIGH Period of SCL Clock Setup Time for a Repeated START Condition Data Hold Time (Notes 9, 10) Data Setup Time (Note 11) Rise Time of Both SDA and SCL Signals (Note 12) Fall Time of Both SDA and SCL Signals (Note 12) Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB CI/O CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 12) 10 0.6 4.0 400 20 + 0.1CB MIN 100 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 20 + 0.1CB 0.9 TYP MAX 400 100 UNITS kHz ms ms ms ms ms ms ns 300 1000 300 300 ns
ns ms pF pF
Note 1: SCL only. Note 2: SDA, INTA, and SQW/INTB. Note 3: ICCA--SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC. Note 4: Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC. Note 5: SQW enabled. Note 6: Specified with the SQW function disabled by setting INTCN = 1. Note 7: Using recommended crystal on X1 and X2. Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 10: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 12: CB--total capacitance of one bus line in pF.
3 of 13
DS1337
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25 C, unless otherwise noted.)
IOSC VS. VCC (SQUARE-WAVE OFF)
DS1337 toc01
IOSC VS. VCC (SQUARE-WAVE ON)
800 750 SUPPLY CURRENT (nA) 700 650 600 550 500 450 400 350
DS1337 toc02
500
850
SUPPLY CURRENT (nA)
450
400
350
300 1.3 1.8 2.3 3.3 3.8 4.3 4.8 VBAT (V)
1.3
1.8
2.3
3.3
3.8
4.3
4.8
VBAT (V)
IOSC VS. TEMPERATURE (SQUARE-WAVE OFF)
VCC = 3.0V 450 SUPPLY CURRENT (nA)
DS1337 toc03
ICCA vs. VCC (SQUARE-WAVE ON)
250 SUPPLY CURRENT (mA) 225 200 175 150 125 100 75
DS1337 toc04
475
275
425 400 375 350 -40 -20 0 20 40 60 80 TEMPERATURE ( C)
50 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V)
OSCILLATOR FREQUENCY vs. VCC
VCC = 0V 32767.70 FREQUENCY (Hz) 32767.65 32767.60 32767.55 32767.50 32767.45 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 VBACKUP (V)
DS1337 toc05
32767.75
5 of 16
DS1337
PIN DESCRIPTION
PIN 1 NAME X1 DESCRIPTION These signals are connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas RealTime Clocks. An external 32.768kHz oscillator can also drive the DS1337. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Interrupt Output. When enabled, INTA is asserted low when the time/day/date matches the values set in the alarm registers. This pin is an open-drain output and requires an external pullup resistor. DC power is provided to the device on these pins. Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pullup resistor. Serial Clock Input. SCL is used to synchronize data movement on the serial interface. Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It is an open-drain output and requires an external pullup resistor. DC power is provided to the device on these pins.
2
X2
3 4 5 6 7 8
INTA
GND SDA SCL SQW/INTB VCC
Figure 1. Recommended Layout for Crystal
5 of 13
DS1337
Figure 2. Timing Diagram
OPERATION
The block diagram in Figure 3 shows the main elements of the DS1337. As shown, communications to and from the DS1337 occur serially over a 2-wire, bidirectional bus. The DS1337 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed.
Figure 3. Block Diagram
6 of 13
DS1337
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
ADDRESS MAP
The address map for the registers of the DS1337 is shown in Table 1. During a multibyte access, when the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On a 2wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Table 1. Timekeeper Registers
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H A1M1 A1M2 A1M3 12/24 BIT 7 0 0 0 0 0 Century 12/24 0 0 0 10 Year 10 Seconds 10 Minutes AM/PM 10hr 10hr Hour 0 BIT 6 BIT 5 10 Seconds 10 Minutes AM/PM 10hr 0 10 Date 10 Mo 10hr 0 0 Date Month Year Seconds Minutes Hour Day Hours Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Alarm 1 Hours Alarm 1 Day Alarm 1 Date Alarm 2 Minutes Alarm 2 Hours Alarm 2 Day Alarm 2 Date A2IE A2F A1IE A1F Control Status BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Seconds Minutes RANGE 00-59 00-59 1-12 +AM/PM 00-23 1-7 00-31 01-12 + Century 00-99 00-59 00-59 1-12 + AM/PM 00-23 1-7 1-31 00-59 1-12 + AM/PM 00-23 1-7 1-31 Seconds Minutes
0AH
A1M4
DY/DT
Day 10 DATE 10 Minutes AM/PM Date Minutes 10hr Hour
0BH 0CH
A2M2 A2M3 12/24
10hr
0DH 0EH 0FH
A2M4 EOSC OSF
DY/DT 0 0 0 0
Day 10 Date RS2 0 RS1 0 Date INTCN 0
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the VOSC.
7 of 13
DS1337
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are illustrated in Table 1. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99-00.
ALARMS
The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h-0Ah. Alarm 2 can be set by writing to registers 0Bh-0Dh. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes--each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2). When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h-06h match the values stored in the time-ofday/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0-5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.
8 of 13
DS1337
Table 2. Alarm Mask Bits
DY/DT X X X X 0 1 ALARM 1 REGISTER MASK BITS (BIT 7) A1M4 A1M3 A1M2 A1M1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match
DY/DT X X X 0 1
ALARM 2 REGISTER MASK BITS (BIT 7) A2M4 A2M3 A2M2 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
ALARM RATE Alarm once per minute (00 seconds of every minute) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match
SPECIAL PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and squarewave output. Control Register (0Eh)
Bit 7
EOSC
Bit 6 0
Bit 5 0
Bit 4 RS2
Bit 3 RS1
Bit 2 INTCN
Bit 1 A2IE
Bit 0 A1IE
EOSC, Enable Oscillator. This bit when set to logic 0 starts the oscillator. When this bit is set to logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. RS2 and RS1, Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
Table 3. Square-Wave Output Frequency
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
INTCN, Interrupt Control. This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
9 of 13
DS1337
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the INTA pin (provided that the alarms are enabled). In this configuration, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied. A1IE, Alarm 1 Interrupt Enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INTA . When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE bit is disabled (logic 0) when power is first applied. A2IE, Alarm 2 Interrupt Enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7 OSF Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 A2F Bit 0 A1F
OSF, Oscillator Stop Flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) 2) 3) 4) The first time power is applied. The voltage present on VCC is insufficient to support oscillation. The EOSC bit is turned off. External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. A1F, Alarm 1 Flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. A2F, Alarm 2 Flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the INTA pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
10 of 13
DS1337
2-WIRE SERIAL DATA BUS
The DS1337 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1337 operates as a slave on the 2-wire bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 4): Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
11 of 13
DS1337
Figure 4. Data Transfer On 2-Wire Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1337 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 5). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. After the DS1337 acknowledges the slave address + write bit, the master transmits a word address to the DS1337. This sets the register pointer on the DS1337. The master may then transmit 0 or more bytes of data, with the DS1337 acknowledging each byte received. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1337 while the serial clock is input on SCL.
12 of 13
DS1337
START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 6). The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. The DS1337 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The DS1337 must receive a "not acknowledge" to end a read.
Figure 5. Data Write: Slave Receiver Mode
Figure 6. Data Read: Slave Transmitter Mode
CHIP INFORMATION
Transistor Count: 10,950 Process: CMOS
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/dallaspackinfo.
13 of 13

▲Up To Search▲

Price & Availability of DS1337

	To Download DS1337 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .